Wednesday, January 25, 2017

IFTLE on Sony, Tessera, SMIC News

IFTLE 319 by Phil Garrou reviews a couple of presentations from this year’s 3D ASIP.

Tetsuo Nomoto, Senior GM of Sony’s mobile imaging systems business, says that the next generation Sony sensors will include stacked DRAM chips to achieve “5X faster scan out and storage data, improve distortion and reduce 1/f bandwidth” and then incorporating a DSP into the stack to 3 Layered modules with customized staked DRAM. The 3-layered paper is to be presented at the next ISSCC.


Sony believes such technologies will improve robotics and robotic manufacturing:


Tessera's Paul Enquist presented their hybrid bonding process. He said that Sony is currently in production with 6um pitch and Tessera is currently capable of 1.6um pitch in demonstration vehicles. The companies feel they are close to pixel level interconnect stege.

Tessera hybrid bonding process

Roc Blumenthal presented SMICs CMOS sensor foundry capabilities:

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