Tuesday, February 07, 2017

Sony Presents 3-Layer Stacked Sensor for Smartphones

Sony announces the development of the industry's first 3-layer stacked CMOS sensor with DRAM for smartphones. The new 20MP 1/2.3-inch sensor minimizes the rolling shutter distortions by providing a 8.33ms-fast readout of the full 20MP of the sensor into the internal 1Gb DRAM.


The high-speed readout capability makes it possible to record up to 1,000 fps (approximately 8x faster than conventional Sony products) super slow motion movies in full HD (1920x1080 pixels).


Sony also publishes a Youtube video showing the new sensor capabilities:



Sony has presented the new sensor at ISSCC 2017. Few slides from the demo session:


Update: A slide on one of the high speed modes added below. There are 4 ADCs per column in order to read 4 rows in parallel and a SF coupled binning:

8 comments:

  1. A master piece, bravo !

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  2. Doesn't the canon new global shutter work in a similar way? So the storage memory is helpful as a buffer but doesn't explain how they increased the read speed. Are there more ADC's per column? How is this different from the RXIV sensor?

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    1. There are 4-row parallel readout with 4 ADCs per column and somewhat objectionable SF-coupled binning mode. A slide explaining the binning mode added.

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  3. Albert Theuwissen - Harvest ImagingFebruary 7, 2017 at 7:05 PM

    This time you are faster Vladimir. I had in mind to post some info on the Harvest Imaging blog, but too late ...

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  4. I understand the 20G red path figure (1000fps x 2MPxFHD x 10bpp), but why is there a 600 Mbps mark on blue path? The MIPI output is assumed to be 4 lane (4x 2.2G or 4x2G) in order to deliver 4K60 (as that alone in UHD size of 8MPx x 60 x 10bpp is 4800 Mbps). Somebody forgot to show the 600 as MB/s? But then it would not be such wow factor as the 20000 to 600 now :) Anyway, rising the output lane count to 10 or 12, one could have continuous operation in high speed mode. And 10-12 lanes are nothing special in SONY's still camera world (yet they still run in LVDS at 600 Mbps, not 2G of course)

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  5. this work must stored compressed image.

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    1. There is 'comp' and 'deComp' in teh block diagram, so I think you are right.

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